In the field of NAND flash memories, as a result of the rapid advance in downsizing of device size for a reduction in cost through enhancement of bit density, cell size has nearly reached a physical limit. Therefore, a stacked nonvolatile memory formed by three-dimensionally stacking memory cells attracts attention as means for attaining higher bit density. As the stacked nonvolatile memory, stacked nonvolatile memories of a metal-oxide-nitride-oxide-semiconductor (MONOS) type and a floating gate type in which a floating gate is formed in a doughnut shape are proposed.
However, in the stacked nonvolatile memory of the MONOS type, reliability of a memory operation is low. It is difficult to realize a multi-value operation such as multi-level-cell (MLC: information for two bits is stored in one memory cell) and triple-level-cell (TLC: information for three bits is stored in one memory cell) universally used in a floating gate structure.
In the stacked nonvolatile memory in which the floating gate electrode film is formed in a doughnut shape, a projection area of a memory cell (corresponding to a cell area in a planar floating gate type structure) is large. The structure and the process of the stacked nonvolatile memory are substantially different from those of a nonvolatile memory of a planar floating gate type widely used in the past. This hinders replacement of the nonvolatile memory of the planar floating gate type in the past with the stacked nonvolatile memory.